1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated integrated circuit products, and, more specifically, to various methods of trimming nanowire structures employed in various semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond. A further improvement upon FinFET devices involves the use of a dielectric isolation material to completely isolate the “fin” channel from one another and the substrate. The isolation material tends to reduce leakage between neighboring FinFET devices as well as decrease leakage current between the source and drain that travels through the substrate in a typical “bulk” FinFET device.
Another form of 3D semiconductor device employs so-called nanowire structures for the channel region of the device. There are several known techniques for forming such nanowire structures. FIGS. 1A-1C are various views of an illustrative 3D device 10 at the point of fabrication wherein the basic nanowire structures 14 have been formed. FIG. 1A is a plan view of the device 10, and FIGS. 1B-1C are cross-sectional views of the device 10 taken where indicated in FIG. 1A.
As shown in FIGS. 1A-1C, the 3D device 10 includes three illustrative nanowire structures 14 that are formed above a semiconductor substrate 12. The ends of the nanowire structures 14 are anchored to portions 16 of the substrate (shown in dashed lines in FIG. 1C). In some cases, the nanowire structures 14 may be formed prior to the formation of a trench isolation region around the device 10. As shown in FIG. 1C, in one embodiment, the nanowire structures 14 may have a generally circular cross-sectional configuration.
In general, as semiconductor devices are scaled to smaller and smaller feature sizes, it is becoming even more important that manufacturing techniques used to make the device have the capability to reliably and repeatedly produce features that have a uniform size and configuration. This is also true for advanced semiconductor devices that employ nanowire structures as the channel region for the device. As with previous types of transistor devices, there is a constant demand to produce very small nanowire structures.
The present disclosure is directed to various methods of trimming nanowire structures employed in various semiconductor devices that may solve or reduce one or more of the problems identified above.